Why sequential consistency

Is there a good reason for doing this? What confused me even further was that in the textbooks on concurrency theory that I could access e. The underlying hardware often has more relaxed memory ordering compared to SC.

For example, the X86 will allow for older stores to be reordered with newer loads for a different address due to store buffers. So instead of having a total order over all loads and stores SC , you only get a total order over all store TSO.

ARM is even more relaxed. And apart from the hardware, the compiler can also reorder instructions if this isn't prohibited. There are also weak memory models. For most engineer it is way too difficult to reason about any other model than SC. Sign up to join this community.

The best answers are voted up and rise to the top. Stack Overflow for Teams — Collaborate and share knowledge with a private group. Create a free Team What is Teams? Learn more. Why sequential consistency model is widely used if it is unsound Ask Question.

Asked 7 months ago. Active 7 months ago. Viewed 81 times. Roscoe, B. The theory and practice of concurrency. Bowman, H. Concurrency theory: calculi an automata for modelling untimed and timed concurrent systems. Gorrieri, R. Introduction to concurrency theory: transition systems and CCS.

Improve this question. Barte Barte 1 1 gold badge 5 5 silver badges 6 6 bronze badges. If it's just a return address, return-address prediction is usually very good so delaying ret 's ability to read it is not much of a problem. So lock or dword [rsp-4], 0 could be worth considering in some cases.

This was before it was known that it might be better than mfence even when mfence was available. All compilers currently use mfence for a stand-alone barrier when it's available. Opposite of Skylake, where it was mfence instead of lock ed instructions that were a problem. But unlike SKL, there's no fix in microcode. This may be why Linux still uses mfence for its mb for drivers, in case anything ever uses NT loads to copy back from video RAM or something but can't let the reads happen until after an earlier store is visible.

In Linux 4. The kernel doesn't use a red-zone even in bit, so the -4 may help avoid extra latency for local vars. Changing mb is riskier because it's harder to test affects drivers , and CPUs have errata related to lock vs.

The only change is the You mean release , I hope. No, that's a compiler barrier only; it prevents all compile-time reordering across it, but doesn't prevent runtime StoreLoad reordering , i. StoreLoad is the only kind of runtime reordering x86 allows.

Using a release fence would not be strong enough it and the release-store could both be delayed past a later load, which is the same thing as saying that release fences don't keep later loads from happening early. A release-acquire fence would do the trick, though, keeping later loads from happening early and not itself being able to reorder with the release store. Related: Jeff Preshing's article on fences being different from release operations.

On x86, all store have a single total order which all cores agree on. Stack Overflow for Teams — Collaborate and share knowledge with a private group.

Create a free Team What is Teams? Collectives on Stack Overflow. Learn more. Why does a std::atomic store with sequential consistency use XCHG? Ask Question. Asked 3 years, 7 months ago.

Active 1 year, 1 month ago. Viewed 2k times. Where a store has an implicit acquire fence. Improve this question.

BartoszKP Leandros Leandros DanielLangr It's not about the fence, but rather about why the whole operation is implemented as an xchg as opposed to a simple mov which is also atomic, assuming the target is correctly aligned. Compiler barrier only prevents reordering at compiler level, not at CPU level.

Add a comment. Active Oldest Votes. Where a store has an implicit acquire fence You mean release , I hope. Or asm volatile "" "memory" ; No, that's a compiler barrier only; it prevents all compile-time reordering across it, but doesn't prevent runtime StoreLoad reordering , i. Improve this answer. Peter Cordes Peter Cordes k 39 39 gold badges silver badges bronze badges. Thanks for the thorough answer, that clears everything up!

I read the great articles from Jeff Preshing, which left me at this question. I got the implicit ordering confused.